Currently all PLLs, except the all-digitally-implemented PLLs, utilize a VCO to provide the clocking means. A VCO is employed, for example, for this purpose in the design of a magnetic recording channel.
A major problem in the design of PLLS is assuring a very tight tolerance for the free-running frequency of the VCO. To achieve this, temperature compensation techniques are often incorporated into the design of the VCO circuitry. However, since the variations in process parameters (such as oxide thickness, threshold voltage, etc.) are statistically independent of each other, the effect on the circuit cannot be fully overcome using design techniques. The VCO free-running frequency can have as much as 30%-50% variation from chip to chip. However, for a PLL to function correctly it is essential that the free-running frequency tolerance be very tight and not vary more than 1%-2%.
Heretofore, the chip-to-chip variation in VCO free-running frequency was resolved by physically modifying the PLL chip by using (1) a laser trim technique involving trimming resistors or capacitors which are on the module substrate and connected to the VCO circuit inside the chip; or (2) a high current zapping technique to blow out resistors on the chip at the wafer level. Both of these techniques are expensive and time consuming, and the high current zapping technique is unreliable for the tight tolerances required for a VCO.
U.S. Pat. No. 4,380,742 describes a circuit for synchronizing the frequency and/or phase of an output frequency signal to reference frequency signal. This phase-locked or frequency locked circuit comprises an oscillator the components of which must be trimmed, as in the prior art. There is no teaching of a combination PLL and FLL circuit which (1) permits setting of VCO free-running frequency without laser trimming, and (2) dynamically adjusts the free-running frequency, if and when the phase error in a PLL as converted to a frequency error by a digital integrator, exceeds the correction range capability of the PLL.
Other frequency synthesizing circuits are described in U.S. Pat. Nos. 4,654,604; 4,672,477; 3,651,422 and 4,543,661. None enable elimination of laser trimming or provide dynamic adjustment of VCO free-running frequency.
There is a need for a method and means for setting the VCO free-running frequency to compensate for different performance characteristics due to process variations and for eliminating the costly laser trimming technique currently used, for example, to set the VCO free-running frequency in a PLL of a magnetic recording channel. In addition, it would be desirable that such a method and means permit frequency to be adjusted dynamically at the system level to compensate for variations in temperature, power supply, drift of components due to aging, or other factors. Such a method and means should also desirably permit the free-running frequency to be changed dynamically by programming that will adjust the frequency ratio to enable use of several different data frequencies with a single predetermined servo or other reference frequency for data banding.